1. Technical Field of the Invention
The present invention relates to scan chains used in testing of integrated circuits, and more particularly to flip-flops for use in such scan chains.
The invention has been developed primarily for use with scan chains for testing system on chip (SoC) circuits, and will be described hereinafter with reference to this application. However, it will be appreciated that the invention can be applied to many other forms of integrated circuitry.
2. Description of Related Art
During testing of system on chip (SoC) designs, a predetermined stream of data is clocked into a serially connected set of D-type flip-flops on the chip. Once all of the data is latched by the relevant flip-flops and therefore available to the relevant inputs throughout the circuit, a suitable clock signal is applied to the circuitry. The results are then clocked out of the scan chain for interpretation.
A prior art multiplexed D-type flip-flop is shown in FIG. 1. It includes a positive-edge triggered flip-flop 10 with an output Q and optional outputs QN (inverted Q) and SO (dedicated scan output). The input to the flip-flop 10 is selected via a multiplexer (MUX) 11, which accepts as inputs D (normal functional data) and TI (scan test input). The mode of the MUX 11 is controlled by global scan enable test signal TE. If TE is low on the rising edge of the clock, then the value on the D input is captured into the flip-flop and made available at Q after a small delay. Conversely, when TE is high on a rising clock edge, the value at TI is clocked into the flip-flop and, again, made available at Q after a small delay.
One difficulty with this arrangement is that SoC designs often include multiple, asynchronous clock domains. In the absence of effort to balance all clock trees in scan mode, an attempt to capture all outputs simultaneously can result in incorrect data being captured due to skew between clocks in different domains. This problem is known as “shoot-through.”
One way of reducing this problem is to restrict test pattern generation tools to only allow one scan clock to capture in a given test cycle. However, this requires an increase in the number of test patterns that need to be generated by the tool, which in turn has a detrimental impact on test vector usage and overall test time.